Effective Dynamic Voltage Scaling through Accurate Performance Modeling

Dynamic voltage scaling (DVS) is widely recognized as an effective way to reduce high CPU power consumption. The technique trades CPU performance for power reduction and energy savings. As a result, there have been many proposals on how to effectively manage a DVS processor to minimize the CPU power consumption while keeping the performance degradation within an acceptable range. Most of these proposals use a simple performanceprediction model which assumes that the execution time will double if the CPU speed is cut in half. Unfortunately, this model overly exaggerates the impact that the CPU speed has on the execution time. It is only in the worst case that the execution time doubles when the CPU speed in halved. In general, the actual execution time is less than double. In addition to addressing the importance of an accurate performance model, we develop such a model and formulate an optimal DVS schedule, which serves as the basis of a new interval-based DVS algorithm. We then evaluate the effectiveness of the algorithm via physical measurements on a notebook computer. This work was supported by the DOE LDRD Program through Los Alamos National Laboratory contract W-7405ENG-36. Available as technical report LA-UR-03-7582. 1.5μ 1μ 0.7μ 0.5μ 0.35μ 0.25μ 0.18μ 0.13μ 0.1μ 0.07μ Chip Maximum Power in watts/cm2 Figure 1: The power density of Intel CPUs.